3.1.1 Dual Clock In this technique it is assumed that delay misses rarely happens, then circuit schedules are designed using minimal delays for critical paths. Pair of alternate clocks, fast and slow, is used. The system normally operates at the fast clock however, when an error is noticed, computation for the input values which is causing error is restarted at the slower clock. Under the premise that delay errors occur for small number of input values, the system can switch back to the faster clock on the next input value. It is obvious that this approach is simple to implement but has small hardware expenses. It can also provide somewhat better performance than worst-case design. 3.1.2 Data Speculation The definition of data speculation states the use of feasible incorrect logic values in dependent computations. The idea behind the concept of approximation is to implement the logic function partially instead completely. Most of the time the partial implementation gives the correct result as compared to the function is implemented completely. This scheme gives fewer gates delay allowing a higher pipeline frequency. Unlike frequency selection, the data speculation scheme can recover from mis-speculation by locally re-executing the incorrect computations only. This type of local error recovery requires both hardware (runtime) and design support. To re-execute incorrect computations, a simple approach is adopted in which computations are restarted from a known correct state. A state is considered to be correct if no computation dependent on the mis-speculated data value has been performed in its predecessors. Computation which now restarted from a correct state can be guaranteed to be as correct.