Nt1310 Unit 5 Lab Report

4.1.6 Flip ops as Counters
As can be seen from Figure 4.7 and Figure 4.8, a T-FF can be implemented using a D-
FF feeding back the negate output /Q to the input D. The input clock to be divided is then provided at the CLK input. Cascading n T-FF stages as shown in Figure 4.8, it is
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possible to divide the input frequency by a factor of 2^n . Based on current requirement
Figure 4.7: FlipFlop of IC, size and availability and operating temperature, the rst combination which is the cascade of divide-by-4, divide-by-10 and divide-by-10 is chosen. The ip op as divide by
4, 10, 40 etc have been simulated with ADS. A divide by 4 ip op employing D ip op is shown next in Figure 4.8. The simulation plot for divide-by-4 (Figure 4.9) is shown
Figure 4.8: Cascaded ip ops

The output frequency of divider gets divided by 4 ie 1.05 GHz.
Since for practical realization, one cannot directly give RF signal directly to frequency divider input pin to avoid huge impedance mismatch. Use of microstrip line[4] in the ter- mination allows for smooth transition of signal from SMA probe to Microstrip and further
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Figure 4.10: Divided output of divide-by-4 ip op to frequency divider pin. The schematic of divide-by-4 with microstrip is shown below in
Figure 4.11. The width and length of microstrip is calculated from line calculator tool of
ADS for the following:
Substrate thickness-0.762 mm
Metal thickness-0.035 mm
Loss tangent-0.0015
Dielectric constant-2.55
Figure 4.11: Divide-by-4 ip op using microtrip line
With microstrip lines inserted at input and output of divider ip ops, the output frequency from divider, for an input frequency of 5GHz is 1.234 GHz, more