Essential Study Guide for VLSI Design Final Exam Review

School

University of California, Riverside**We aren't endorsed by this school

Course

EECS 168

Subject

Electrical Engineering

Date

Dec 11, 2024

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Uploaded by MagistrateNarwhal4033

Modern VLSI Design 4e: Chapter 1www.ece.ucr.edu/~stanEmail: stan@ece.ucr.eduEECS 168: Final Review Falll 2023

Modern VLSI Design 4e: Chapter 1Time and locationTime:Wed, Dec. 11, 12:00 p.m. –Dec. 12, 11:59 p.m (24 hour window)Same format of two midterms–online examTimed exam: 180 minutes (3 hours) is allowed once you start theexam. Please do not save and leave the exam until you finish.Load the images of the answers to each questions.Ask question in piazza during the exam time.Location: Virtual via canvas

Modern VLSI Design 4e: Chapter 1PolicyOpen bookOpen notesCalculator is needed and allowedPlease show all the steps, which will help you to score better.

Modern VLSI Design 4e: Chapter 1Coverage for finalChapter 1, Digital system and VLSIChapter 2, Fabrication and DevicesChapter 3, Logic GatesChapter 4, Combinational Logic Networks Chapter 7, Floorplaning Chapter 8, HDL Verilog language for combinational logicsTotal 8 questions with emphases on the chp4, chap7, chp8. Coverage from Chapter 2, 3, 4, 7 and HDL VerilogTotal 8 questions cover all the chapters or chapter sections mentioned with emphasis on the chapter 4, 7 and 8

Modern VLSI Design 4e: Chapter 1Topics in Chapter 1-2MOSFET characteristicsWire resistance and capacitanceLayout and stick diagrams

Modern VLSI Design 4e: Chapter 1MOSFET–metal-oxide-semiconductor field transistorN-type MOSFET (NMOS)–Carrier: electrons (negative charge)–Carriers flow from source to drain–Current direction: drain to sourceP-type MOSFET (PMOS)–Carrier: holes (positive charge)–Carriers flow from source to drain–Current direction: source to drainMOSFETNMOS, ON-state

Modern VLSI Design 4e: Chapter 1MOSFET FunctioningFrom WikipediaNMOS

Modern VLSI Design 4e: Chapter 1Drain Current CharacteristicsNMOSPMOS: Similar to NMOS, but Vgs, Vds, Vth, Id in the opposite direction (for example, Vgs_pmos = -Vgs_nmos)Linear region (Vds< Vgs- Vt):–Id= k’(W/L)[(Vgs- Vt) Vds - 0.5Vds2]Saturation region (Vds>= Vgs- Vt):–Id= 0.5k’(W/L)(Vgs- Vt) 2–Drain current independent of Vds

Modern VLSI Design 4e: Chapter 1Wire ResistancenResistance of any size square is constant (uniform in thickness t):nSheet resistance : a measure of resistances in thin films that are normally uniform in thicknessRGeometry for defining resistivity (left) and sheet resistance (right). currentcurrentR=rtR=rLS=rLtW=RLWSheet resistance is independent of thickness tUnit: common unit is "ohms per square" (denoted "Ω/sq" or ), which is dimensionally equal to an ohm, but is exclusively used for sheet resistanceW/

Modern VLSI Design 4e: Chapter 1Wire ResistancePoly-Silicon, R☐= 8Ω/☐R=R☐*18λ/3λ=48ΩWire width: 3λWire length: 18λ

Modern VLSI Design 4e: Chapter 1Corner ResistanceL1L2WSquare corner (constant width)Rcorner=0.5R☐R=R☐*L1/W+Rcorner+R☐*L2/WL1L2W2W1W1!= W2Rcorner=R☐(0.46+0.1*W_large/W_small)R=R☐*L1/W1+Rcorner+R☐*L2/W2

Modern VLSI Design 4e: Chapter 1Poly/metal wire capacitanceTwo components:–parallel plate;–fringe.platefringe

Modern VLSI Design 4e: Chapter 1Stick Diagrams

Modern VLSI Design 4e: Chapter 1Design RulesInterface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line width–scalable design rules: 𝜆 (lambda) parameter –absolute dimensions (micron rules)

Modern VLSI Design 4e: Chapter 1Intra-Layer Design RulesMetal2431090 WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62Hole

Modern VLSI Design 4e: Chapter 11253TransistorTransistor Layout

Modern VLSI Design 4e: Chapter 1Vias and Contacts121ViaMetal toPoly ContactMetal toActive Contact1254322

Modern VLSI Design 4e: Chapter 1Chapter 3Chapter 3.3 Static Complementary Gates–Design of complicated CMOS gates»Design of the pulldown and pullup networks from given logic expressions»Complicated gates such as AOI21»How to size the pulldown and pullup networks so that the pulldown and pullup time times are same.–Logic level » Definition of delay and transition times for a gate and expressions (-log(0.5)RC or -log(0.1)RC).

Modern VLSI Design 4e: Chapter 1Chapter 3Chapter 3.3 Static Complementary Gates–The gate delay model and how to compute the gate delay»The gate resistance Rt= L/W Rn,p, Rn,p is effective resistance.»How to size the pullup and pulldown networks to meet some transition time requirements.»How to compute the rise and fall times for some gates with given W/L and driving some wires.

Modern VLSI Design 4e: Chapter 1Alterative Gate CircuitsPseudo-nMOS logic–What is the pros and cons of this circuitDomino logic–Also call the pre-charged logic–What is the pros and cons of this circuit

Modern VLSI Design 4e: Chapter 1Chapter 3Chapter 3.7 Interconnect delays–Elmore delay model »Elmore delay computation for a transmission line ½ 𝑟𝑐 𝑛 (𝑛 + 1)»How to compute a Elmore delay for a given RC network.

Modern VLSI Design 4e: Chapter 1Chapter 4Chapter 4.2 Standard Cell Design–The concept of standard cell design and layout–The channel density concept»how to compute the channel density–The left edge algorithm for channel routing»the vertical constraints and routability»The dogleg routing technique

Modern VLSI Design 4e: Chapter 1Chapter 4Chapter 4.3 Logic and Interconnect Design–The delay models»The critical paths, glitch»The cutset through critical paths, false paths, –Buffer insertion in a long wire»Number of buffers needed, the k value»The size of buffers, the increasing rate: h value.–Buffer insertion in a RC tree»How compute the required time for the source»How to compute the required time when a buffer is inserted.

Modern VLSI Design 4e: Chapter 1Chapter 4Extract the schematic from a complicated gate layout.Find the W/L of some MOS devices from the layout.

Modern VLSI Design 4e: Chapter 1Chapter 4»How to compute least delay for a network in terms of unit time (delay of the minimum inverter), d=gh+p or d=Df+P for a path.»How to size the gates along path to achieve the least delay based on the results of logic effort

Modern VLSI Design 4e: Chapter 1One example for logic effort

Modern VLSI Design 4e: Chapter 1Chapter 4–The stuck-at-1/0 (S-A-0/1) fault concept and testing vector design for stuck-at-faults.»Controlling the gate having fault to drive to it desired value»Observing the results from the primary outputs.

Modern VLSI Design 4e: Chapter 1Verilog HDL languageThe basic concepts of VerilogCan write a simple Verilog code for combinational logic using given primitive gates.Can write the Verilog codes for combinational logic using continuous assignment statement. Can draw the logic schematic from a given Verilog codes.Understand the difference between block and non-block assignment.

Modern VLSI Design 4e: Chapter 1Verilog HDL languageVerilog modeling–Structure based modeling using the gate primitives and existing user-defined modules–Behavioral modeling »Continuous assignment for combinational circuits»FSM for sequential logic models–“always” and ”initial” statement for concurrency modeling»Blocked by event, delay (#), wait statements

Modern VLSI Design 4e: Chapter 1Difference between different assignment statementsContinuous assignment –Example: assign a = b | (c&d);–Driving net only, change right away if input changesProcedural assignment –Inside initial and always statement, value assigned when control is transferred to the statement–Has blocking (=) and non blocking (<=) assignments–“<=“ updates its LHS value only when all the RHS of “<=“ statements waiting for same edge have been calculated (modeling the sequential circuit behaviors)–Driving registers only@(posedge clock) beginm= 3;n=75;n <= m;r = n;….What is value of r?Answer is r = 75

Modern VLSI Design 4e: Chapter 1Difference between different assignment statements (cont’d)@(posedge clock) beginm = 3; // (1) Blocking assignment: m is now 3 immediately.n = 75; // (2) Blocking assignment: n is now 75 immediately.n <= m; // (3) Non-blocking assignment: Schedules n to be updated to m’s value (3), but only after all blocking assignments in this time step are done.r = n; // (4) Blocking assignment: At this point, n still holds the old value (75) since the non-blocking assignment to n hasn’t taken effect yet.end@(posedge clock) beginm= 3;n=75;n <= m;r = n;….What is value of r?Answer is r = 75

Modern VLSI Design 4e: Chapter 1Chapter 7 FloorplaningBasic physical design steps in floorplanning–Block placement, global routing, channel/switching box routing, p/g routing, clock tree routingConcept of channels, channel identification (including switching boxes), channel utilization, line probe routingChanel graph, the channel routing dependency, the routing ordering.Power grid routing–Planar p/g network, IR drop and Ldi/dt problems, decoupling capClock tree routing/synthesis–H-tree, balanced-tree, zero-skew routing

Modern VLSI Design 4e: Chapter 1Channel routing graph and routing order exampleaa12For wire ‘a’, we need to route segment 1 in channel c1 first, then we can route segment 2 in channel c2, as a result, we have the c2 dependence on c1. The second terminal on wire ’a’ (pink one) can only be determined from channel c1, not from channel c2 as all the terminals in a channels on both sides much be determined before routing.

Modern VLSI Design 4e: Chapter 1