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Understanding Datapath and Control Signals in MIPS Instructions

School
Florida State University**We aren't endorsed by this school
Course
CDA 3100
Subject
Computer Science
Date
Dec 11, 2024
Pages
8
Uploaded by MagistrateTeamPorpoise42
Datapath and Control for add $t0, $t1, $t2 Instruction[31-0]: 000000 01001 01010 01000 00000 100000add $t0, $t1, $t2 # the data in $t1 and $t2 are 32 and 50, respectivelyControl signal:RegDst = ALUSrc = MemtoReg = RegWrite =Branch = MemRead MemWrite = ALUOp =
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Datapath and Control for add $t0, $t1, $t2 Instruction[31-0]: 000000 01001 01010 01000 00000 100000add $t0, $t1, $t2 # the data in $t1 and $t2 are 32 and 50, respectively0000000100101010010003250825082100000Control signal:RegDst = 1, Destination register comes from the rd field.ALUSrc = 0, Second ALU operand is the output from Read Data 2. MemtoReg = 0, Value of register Write Data is from ALU.RegWrite = 1, Write Register is written to with Write Data. Branch = 0, R format is not branch instruction. MemRead = MemWrite = 0, R format does not need the data memory.ALUOp = 10, addition instruction.
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Datapath and Control for lw $t0, 16($t1)Instruction[31-0]: 100011 01001 01000 0000 0000 0001 0000lw $t0, 16($t1) # the data in $t1 is 16; the data in the memory unit indicated by the calculated address is 50Control signal:RegDst = ALUSrc = MemtoReg = RegWrite =Branch = MemRead MemWrite = ALUOp =
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Datapath and Control for lw $t0, 16($t1)Instruction[31-0]: 100011 01001 01000 0000 0000 0001 00001000110100101000lw $t0, 16($t1) # the data in $t1 is 16; the data in the memory unit indicated by the calculated address is 501632Control signal:RegDst = 0, Destination register comes from the rt field.ALUSrc = 1, Second ALU operand is immediate field.MemtoReg = 1, Value of register Write Data is memory Read Data.RegWrite = 1, Write Register is written to with Write Data. Branch = 0, lw is not branch instruction. MemRead = 1, we read the data from the data memoryMemWrite = 0, we do not write data to the data memory ALUOp = 00, lw instruction00000000000100000000 0000 0000 0000 0000 0000 0001 00005050
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Datapath and Control for sw $t0, 16($t1)Instruction[31-0]: 101011 01001 01000 0000 0000 0001 0000sw $t0, 16($t1) # the data in $t0 and $t1 are 8 and 16, respectivelyControl signal:RegDst = ALUSrc = MemtoReg = RegWrite =Branch = MemRead = MemWrite = ALUOp =
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Datapath and Control for sw $t0, 16($t1)Instruction[31-0]: 101011 01001 01000 0000 0000 0001 00001010110100101000sw $t0, 16($t1) # the data in $t0 and $t1 are 8 and 16, respectively1632Control signal:RegDst = XALUSrc = 1, Second ALU operand is immediate field.MemtoReg = XRegWrite = 0, NoneBranch = 0, lw is not branch instruction. MemRead = 0, we do not read the data from the data memoryMemWrite = 1, we write data to the data memory ALUOp = 00, sw instruction00000000000100000000 0000 0000 0000 0000 0000 0001 000088
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Datapath and Control for beq $t1, $t2, immedInstruction[31-0]: 000100 01001 01010 0000 0000 0000 0100beq $t1, $t2, immed # the data in $t1 and $t2 are 4 and 5, respectively. Immed is 4Control signal:RegDst = ALUSrc = MemtoReg = RegWrite =Branch = MemRead MemWrite = ALUOp =
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Datapath and Control for beq $t1, $t2, immedInstruction[31-0]: 000100 01001 01010 0000 0000 0000 01000001000100101010beq $t1, $t2, immed # the data in $t1 and $t2 are 4 and 5, respectively. Immed is 440Control signal:RegDst = XALUSrc = 0, Second ALU operand is Read Data 2.MemtoReg = XRegWrite = 0, NoneBranch = 1, beq instructionMemRead = 0, we do not read the data from the data memoryMemWrite = 0, we do not write data to the data memory ALUOp = 01, beq instruction00000000000001000000 0000 0000 0000 0000 0000 0000 01005
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