Designing a 3-Bit Adder/Subtractor Circuit with Overflow

School

Iowa State University**We aren't endorsed by this school

Course

CPR E 281

Subject

Electrical Engineering

Date

Dec 12, 2024

Pages

Uploaded by ProfessorBookMule27

En Subtraction: 7 -3 =4 Addition: 4 + (-7) = -3 11001 51 Ignore 0 + 00100 11001 011101 \('L \(‘ \(o add /5€ Yo 3-bit adder Clop —P [ - “ Sy Tonare o Ol wv ~l Yn-1 Add /Sub Wwo control Xn-1 % Q W, v ] 1 Yy \ Y f A4 [ -bit adder w2 J e Sn-1 5 5 w3 H >_ — . A s Overflow Detection: 5-bits s Add /Sub Carry, control in J cary out a) Full Adder (FA) 1 t [ ] ] EAENE Y xn\/y‘ AR AR B3 A3 B2 A2 B1 A1 BO A0 o 5-bit adder l l l l l l Ss S ) 5 ) ‘ [T T 1 Ful [ €3 | Fun | C2 | Fun [ €1 | Ful |cin Adder Adder Adder Adder l/ overtlow Carry S3 s2 s1 so | - - out X4Y484+X4Y484 Clock, — ;i =Xx®y:® ¢ S 1 Civ1 =(Xx;®DYy;)C;i + X, y; ci+1 b) 4-bits Ripple Carry Adder (a) Let A=Az A1 A¢ and B=Bz B1 Bo be two 3-bit binary numbers in 2’s complement representation. You are given three full-adders, one NOT gate, and seven XOR gates. Your task is to design a circuit that can perform two different arithmetic operati The operation is selected by one of the inputs to this circuit that is called S. When S=0 the 3-bit result R= Rz R1 Ry is equal to A-B. Alternatively, when S=1 the result is B-A. The circuit must also detect if an overflow has occurred. Draw the wiring diagram for your circuit below. Clearly label all inputs, outputs, and pins. B2 A’ﬂ» Py 4 e Cl sl s HA c Xi e— Y; —— HA c Cirl (a) Block diagram c; \‘_\ L " A 3-to-8 decoder using two 2-to-4 dec A 1-to-4 demultiplexer built with a 2-to-4 decoder with enable "o " BOY Yo "1 ! i b4l N p23 po) w 1 "2 e » 0 D: 0 0| . A 4-to-1 multiplexer & Lo nb— | . o P built using a 2-to-4 decoder w, Vs . p——— = D % P » " Nr—— H) 5 p— A barrel shifter circuit D Bl S| Sg Y3 Y2V Yo |,_|Di y3 Wy Wy W, W, D g (1) w; wi w; w? 1 : " d , F2, F1, and Fo. The equations 1o woowe W w for the outputs are: RS S H H H H F2=F1=(S1&S0)[($1 &%) (@) Tt tale Hold / Shift-Right Circuit , o w3 w wy o 1 ] .. [ 4-bit input fi 7 fi —7 fi —7 s The Adder / Subtractor Sl_% | yu— — 0 ["’3 "2 " WO] 0 9 sub o | ’ | \+—|+—\+—‘+—‘ | Vi X Yo X Ys X Yo X Vs X Yo X2 Yy X Yo X y V- y Ay ’ " " " Pl o7 Pl o7 Pl 7 Pl 7 X v T LI I I O O O . i 1. Label all inputs, output circuit. (7p) J.l J.l -]._I- ll J.L -LL J.l b 0 it | | | 1 v 0 Yo ", > I [ys Y2 ) yo] k I_ : En wy wy Yo ¥y Yy V3 put 0 1 00 1000 " ; o , 101 0100 i " 0"_|} Y2 110 001 0 Rel 1 1.1 00 01 e LS o 0 00 0 0 4 00—130— »3 i o ,—_)E >— overflow (a) Truth table (b) Graphical symbol carry 281 CPU 0 T T x indicates that it does not matter what the value of this variable is for this row of the truth table

Basic Latch Basic Latch Gated SR latch with NOR gates (with NOR Gates) (with NAND Gates) ® o kS ®| ey Clock is used for the D Flip-Flop, R 3 0 = = | Qnochange) but Clk is used for each D Latch Q‘l Qa Clk 1 0 0 Q(7) (no change) S Q 1 0 1 0 — . 5 1 1 0 1 Master Slave 111 % (undesirable) I Qm | Q, ’ — Clk L j bQ - Q . Clk| Q s e R ’ Gated SR latch with NAND gates - Clock k Q N Clk 8 R | Qe+ 1) R Q o - o |® N Q, Qs s R| Q. Q Q 0 x x Q(1) (no change) 0 0/1 10 (mochange) Latch 0 0 |01 10 (nochange) Latch ik 10 0 | Q)(nochange) 0 0 1 Reset o 1] o 1 Reset oot 0 1 10 Set o1 o Set — oo ! . 1 Undesirable 1o ] Undesirable Q 1 11 = (undesirable) R Characteristic tables are the same Circuit Diagram and Characteristic Table cijrcuit Diagram for the Gated D Latch for the Gated D Latch (with the latch implemented using NORs) D Q Oy | - o Clk D | Q(t+1) Cik Q - KR Q 1 1 1 R | D Flip Flop Constructing a Master-Slave D Flip-Flop Master-Slave D Flip-Flop Positive-Edge-Triggered Input Output From one D Latch and one Gated SR Latch . (This version uses one less NOT gate) MaSter-Slave D FIIp-FlOp D Q Q/\ SMaster Latch Slave Latch . _ O 0 1 ‘Data) s I Master Slave o @ ° fiqm L e R > ol —le , 1 1 0 lock cK Q Cik Q Q o . Zlock TDV ck Q ’, Cik Q Q - B, The Complete Wiring Di f - i Positive-Edge-Triggered D Flip-Flop e Lomplete Wiring Diagram for a ;:)‘:ltcl:\?eTEp:iegtee-"I"! :;I;egr:;agr;:';_f;;p with Asynchronous Clear and Preset a Negative-Edge-Triggered D Flip-Flop preset_n b Clock - ’ Q Q Clock Clock —] Y 3 Q clear_n Dc The Complete Wiring Diagram for Positive-edge-triggered D flip-flo itive- -Tri ip- with asynchrsc’)nougsgCIear andpPresF:at Negative-Edge-Triggered D flip-flop aFosifveScasiriggered T Flip-Fiop with asynchronous Clear and Preset Preset_n The Complete Wiring Diagram for a Negative-Edge-Triggered T Flip-Flop e C © D L 6 [ 3 5 Clock Clear_n (@) Gircuit [>o T-FlipFlop A The Complete Wiring Diagram for a Positive-Edge-Triggered JK Flip-Flop The Complete Wiring Diagram for a Negative-Edge-Triggered JK Flip-Flop Clear_n T Q(t E 1) NextState Q(¢) How ; 1 a( t) TOGGLE o ) vraw we comprere wirmg diagram for a 1-to-2 demultiplexer using only NAND gates. J K Q (t + 1 ) Clearly label all inputs and outputs. Wp Yo Same State’/HOLD () () Q (t) RESET () 1 setr 1 0 Toaale 1 1 Ql