Understanding Digital CMOS Design: MOSFET Configurations
School
Brigham Young University, Idaho**We aren't endorsed by this school
Course
ECEN 390
Subject
Electrical Engineering
Date
Dec 12, 2024
Pages
2
Uploaded by ProfessorOpossumMaster1110
Digital CMOS HW (18 points)(jas, Digital CMOS HW.docx, 8/10/2024)Clearly indicate answers and include units for numeric answers, using 3 or 4 significant figures. Show at least the major steps of your work so that if necessary partial credit can be awarded.1.The adjacent circuit shows an n-channel enhancementmode MOSFET configured as a pull-up transistor with R1representing a very large resistance associated with digitalCMOS. In your own words and using complete sentences,explain why an n-channel enhancement mode MOSFET isa poor digital pull-up transistor, referencing the adjacentcircuit as necessary. (3 Points.)The use of an n-channel enhancement-mode MOSFET as apull-up transistor is suboptimal because it fails to deliver the required voltage levels and logical consistency in digital CMOS circuits.2.The adjacent circuit shows a p-channel enhancementmode MOSFET configured as a pull-down transistor withR1 representing a very large resistance associated withdigital CMOS. In your own words and using completesentences, explain why a p-channel enhancement modeMOSFET is a poor digital pull-down transistor. (3Points.)Its because an n-channel MOSFET is generally preferredas a pull-down transistor in digital circuits because itoperates more efficiently and with lower resistance in thisconfiguration.3.Determine the widths of the n-channel enhancement modeMOSFETs in the adjacent digital logic circuit necessary toprovide the same fall time as an inverter with the n-channel pull-down transistor sized at W/L. Then, givenµn/µp= 2 for the CMOS process, size the p-channel
enhancement mode MOSFETs to provide for equal rise and fall times. Your answer should include the relative width W, but not the relative length L. (4 Points.) nMOS Pull-Down Widths = 3WpMOS Pull-Up Widths = 6W4.Determine the widths of the n-channel enhancement modeMOSFETs in the adjacent digital logic circuit necessary toprovide the same fall time as an inverter with the n-channel pull-down transistor sized at W/L. Then, givenµn/µp= 2 for the CMOS process, size the p-channelenhancement mode MOSFETs to provide for equal riseand fall times. Your answer should include the relativewidth W, but not the relative length L. (4 Points.) nMOS Pull-Down Widths = 1WpMOS Pull-Up Widths = 6W5.Complete the Out column of the truthtable below for the adjacent CMOS logicgate. (4 Points.) BAOut001011101110