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EE100A-lecture16

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University of California, Riverside**We aren't endorsed by this school
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EE 100A
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Electrical Engineering
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Dec 17, 2024
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36
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Example 7.7Q: We need to analyze the circuit of Fig. 7.30(a) to determine the voltage gain and the signal waveforms at various points. The capacitor CC1is a coupling capacitor whose purpose is to couple the signal vito the emitter while blocking dc. In this way the dc bias established by V+and Vβˆ’together with REand RCwill not be disturbed when the signal viis connected. For the purpose of this example, CC1will be assumed to be very large so as to act as a perfect short circuit at signal frequencies of interest. Similarly, another very large capacitor CC2is used to couple the output signal vOto other parts of the system. You may neglect the Early effect.63EE100A Wang UCR
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Example 7.7 Solutionβ€’Step-1: DC analysis for Q-pointοƒΌPNP = active mode, VE= |VBE| = 0.7Vβ‡’BCJ = Off, PNP = active mode64EE100A Wang UCR𝐼𝐼𝐢𝐢=𝑉𝑉+βˆ’ 𝑉𝑉𝐢𝐢𝑅𝑅𝐢𝐢=10𝑉𝑉 βˆ’0.7𝑉𝑉10π‘˜π‘˜Ξ©= 0.93π‘šπ‘šπ΄π΄π›Όπ›Ό=𝛽𝛽𝛽𝛽+ 1=100100 + 1= 0.99𝐼𝐼𝐢𝐢=𝛼𝛼𝐼𝐼𝐢𝐢= 0.92π‘šπ‘šπ΄π΄π‘‰π‘‰πΆπΆ=π‘‰π‘‰βˆ’+𝐼𝐼𝐢𝐢𝑅𝑅𝐢𝐢=βˆ’10𝑉𝑉+ 0.92π‘šπ‘šπ΄π΄Γ—5π‘˜π‘˜Ξ©=βˆ’5.4𝑉𝑉
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Example 7.7 Solutionβ€’Step-2: acsmall-signal analysis for gainοƒΌRemove independent DCsources, οƒΌCalculate small-signal circuit model parametersοƒΌReplace BJT by small-signal modelοƒΌac circuit analysis65EE100A Wang UCR𝑔𝑔𝑔𝑔=𝐼𝐼𝐢𝐢𝑉𝑉𝑇𝑇=0.92π‘šπ‘šπ΄π΄25π‘šπ‘šπ‘‰π‘‰= 36.8π‘šπ‘šπ΄π΄/π‘‰π‘‰π‘Ÿπ‘Ÿπ‘π‘=𝑉𝑉𝑇𝑇𝐼𝐼𝐢𝐢=25π‘šπ‘šπ‘‰π‘‰0.93π‘šπ‘šπ΄π΄= 27.2Ξ©π‘Ÿπ‘Ÿπœ‹πœ‹=𝛽𝛽𝑔𝑔𝑔𝑔= 2.72π‘˜π‘˜Ξ©π΄π΄π‘£π‘£=𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=βˆ’π›Όπ›Όπ‘–π‘–π‘π‘π‘…π‘…πΆπΆβˆ’π‘–π‘–π‘π‘π‘Ÿπ‘Ÿπœ‹πœ‹=182𝑉𝑉/𝑉𝑉
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Example 7.7 Solutionβ€’Step-2: acsmall-signal analysis for gainοƒΌacinput vi= vebοƒΌFor small signals, let vi(t) swing peak οƒΌThus, output swing peak, vO= vC66EE100A Wang UCR�𝑉𝑉𝑖𝑖=10π‘šπ‘šπ‘‰π‘‰οΏ½π‘‰π‘‰π‘‚π‘‚=�𝑉𝑉𝑖𝑖𝐴𝐴𝑣𝑣=10π‘šπ‘šπ‘‰π‘‰Γ— 182 = 1.82𝑉𝑉
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Small-Signal Analysis on Direct Circuit Diagram‒Direct circuit analysis without replacing a transistor by its small-signal circuit modelInsightinto signal transmission pathExample 7.5 (steps)67EE100A Wang UCR
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Small-Signal Analysis on Direct Circuit Diagram‒Direct circuit analysis without replacing a transistor by its small-signal circuit modelExample 7.768EE100A Wang UCR
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Summary on Circuit Analysis‒Circuit analysis stepsSeparate DCand accircuit analysis69EE100A Wang UCR
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Summary on Circuit Analysisβ€’Small-signal models for MOSFET70EE100A Wang UCR
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Summary on Circuit Analysisβ€’Small-signal models for BJT71EE100A Wang UCR
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Basic Amp Circuit Configurationsβ€’Three basic circuit configurations:οƒΌOne common terminal groundedοƒΌ2-port network with one grounded terminal being commonβ€’MOSFETοƒΌCS – common-sourceοƒΌCG – common-gateοƒΌCD – common-drainβ€’BJTοƒΌCE – common-emitterοƒΌCB – common-baseοƒΌCC – common-collectorβ€’Ignoring DC biasing in acanalysis72EE100A Wang UCR
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Basic Amp Circuit Configurationsβ€’Characterize amplifier circuits in generalExample Amp circuit:οƒΌAmplifier functional blocko2-port equivalent circuit modelοƒΌFed by an open-circuit V-source (vsig, internal-R, Rsig)oSignal source: a β€œreal” source, or Thevenin equivalent of proceeding stage οƒΌLoad of Amp:RLoRL= a β€œreal” load, or,oRL= Rinof the following stage73EE100A Wang UCR
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Basic Amp Circuit Configurationsβ€’Characterize amplifier circuits in generalExample Amp circuit:οƒΌAmp block replaced by its equivalent circuit modelo2-port equivalent circuit modelοƒΌKey parameters for Amp circuit:oInput Resistance, Rin(loading effect on the signal source)Input signal (vi) to Ampβ€’For a unilateral circuit (no feedback), Rinis independent of RLRin& Rsigdivides Vsig(loading)74EE100A Wang UCR𝑅𝑅𝑖𝑖𝑛𝑛≑𝑣𝑣𝑖𝑖𝑖𝑖𝑖𝑖𝑣𝑣𝑖𝑖=𝑅𝑅𝑖𝑖𝑛𝑛𝑅𝑅𝑖𝑖𝑛𝑛+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔
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Basic Amp Circuit Configurationsβ€’Characterize amplifier circuits in generalExample Amp circuit:οƒΌKey parameters:oOpen-circuit V-GainoOutput Resistance, ROLooking into output port with vi= 0 not dependent on RsigGeneral derivation using vx,ix75EE100A Wang UCR𝐴𝐴𝑣𝑣𝑝𝑝≑�𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖𝑅𝑅𝐿𝐿=βˆžπ‘…π‘…π‘‚π‘‚β‰‘π‘£π‘£π‘‚π‘‚π‘–π‘–π‘‚π‘‚|𝑣𝑣𝑖𝑖=0=𝑣𝑣𝑔𝑔𝑖𝑖𝑔𝑔
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Basic Amp Circuit Configurationsβ€’Characterize amplifier circuits in generalExample Amp circuit:οƒΌKey parameters:o(Avovi) & (RO) represent the Thevenin equivalent circuit for the Amp outputcircuit blockvs= Avovi& Rs=ROoRO(i.e., RS) andRLdivides Avoviovi-to-vOV-gain including RL(= finite)Avcalled Gain Proper76EE100A Wang UCR𝐴𝐴𝑣𝑣≑�𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖𝑅𝑅𝐿𝐿=𝑓𝑓𝑖𝑖𝑛𝑛𝑖𝑖𝑑𝑑𝑐𝑐=𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂𝐴𝐴𝑣𝑣𝑝𝑝𝑣𝑣𝑂𝑂=𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂𝐴𝐴𝑣𝑣𝑝𝑝𝑣𝑣𝑖𝑖
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Basic Amp Circuit Configurationsβ€’Characterize amplifier circuits in generalExample Amp circuit:οƒΌKey parameters:oOverallV- gain, vsig-to-vOV-gain withoutRLoOverallvsig-to-vOV-gain includingRL77EE100A Wang UCR𝐺𝐺𝑣𝑣≑�𝑣𝑣𝑂𝑂𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔𝑅𝑅𝐿𝐿=βˆžπΊπΊπ‘£π‘£β‰‘οΏ½π‘£π‘£π‘‚π‘‚π‘£π‘£π‘”π‘”π‘–π‘–π‘”π‘”π‘…π‘…πΏπΏβ‰ βˆž=𝑅𝑅𝑖𝑖𝑖𝑖𝑅𝑅𝑖𝑖𝑖𝑖+𝑅𝑅𝑔𝑔𝑖𝑖𝑔𝑔𝐴𝐴𝑣𝑣𝑝𝑝𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂
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Basic Amp Circuit Model: Alternativeβ€’Alternativeequivalent circuit for convenienceοƒΌShort-Circuit Transconductance GainoOpen-Circuit V-gain78EE100A Wang UCRπΊπΊπ‘”π‘”β‰‘οΏ½π‘–π‘–π‘‚π‘‚π‘£π‘£π‘–π‘–π‘£π‘£π‘œπ‘œ=0𝐴𝐴𝑣𝑣𝑝𝑝≑�𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖𝑅𝑅𝐿𝐿=∞=𝐺𝐺𝑔𝑔𝑅𝑅𝑝𝑝
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Basic Amp Circuit Configurations: CS/CEβ€’MOSFET CS amplifierοƒΌSignal source: vsig, RsigοƒΌRDis part of amplifierοƒΌRD||RLοƒΌSolution oInputoV-gain Thus oOutput 79EE100A Wang UCR𝑅𝑅𝑖𝑖𝑛𝑛≑𝑣𝑣𝑖𝑖𝑖𝑖𝑖𝑖=βˆžπ΄π΄π‘£π‘£π‘π‘β‰‘π‘£π‘£π‘‚π‘‚π‘£π‘£π‘–π‘–=βˆ’π‘”π‘”π‘”π‘”π‘…π‘…π·π·= βˆ’πΊπΊπ‘”π‘”π‘…π‘…π·π·π‘£π‘£π‘–π‘–=𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔=𝑣𝑣𝑔𝑔𝑠𝑠𝑖𝑖𝐺𝐺= 0𝑣𝑣𝑂𝑂=βˆ’π‘”π‘”π‘”π‘”π‘£π‘£π‘”π‘”π‘ π‘ π‘…π‘…π·π·π‘…π‘…π‘‚π‘‚=𝑅𝑅𝐷𝐷
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Basic Amp Circuit Configurations: CS/CEβ€’MOSFET CS amplifieroIncludeRLoOverall vsig-to-vOV-gain includingRL80EE100A Wang UCRπΊπΊπ‘£π‘£β‰‘οΏ½π‘£π‘£π‘‚π‘‚π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”π‘…π‘…πΏπΏβ‰ βˆž=βˆ’π‘”π‘”π‘”π‘”(𝑅𝑅𝐷𝐷βˆ₯ 𝑅𝑅𝐿𝐿)𝐴𝐴𝑣𝑣=𝐴𝐴𝑣𝑣𝑝𝑝𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂=βˆ’π‘”π‘”π‘”π‘”(𝑅𝑅𝐷𝐷βˆ₯ 𝑅𝑅𝐿𝐿)𝑣𝑣𝑖𝑖=𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔
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Basic Amp Circuit Configurations: CS/CEβ€’BJT CE amplifierοƒΌSignal source: vsig, RsigοƒΌRCis part of amplifierοƒΌRC||RLοƒΌSolution oInputoV-gain Thus oOutput 81EE100A Wang UCR𝑅𝑅𝑖𝑖𝑛𝑛≑𝑣𝑣𝑖𝑖𝑖𝑖𝑖𝑖=𝑣𝑣𝑖𝑖𝑖𝑖𝑏𝑏=π‘Ÿπ‘Ÿπœ‹πœ‹π΄π΄π‘£π‘£π‘π‘β‰‘π‘£π‘£π‘‚π‘‚π‘£π‘£π‘–π‘–=βˆ’π‘”π‘”π‘”π‘”π‘…π‘…πΆπΆ= βˆ’πΊπΊπ‘”π‘”π‘…π‘…πΆπΆπ‘£π‘£π‘–π‘–=π‘£π‘£πœ‹πœ‹π‘–π‘–π΅π΅β‰ 0𝑣𝑣𝑂𝑂=βˆ’π‘”π‘”π‘”π‘”π‘£π‘£πœ‹πœ‹π‘…π‘…πΆπΆπ‘…π‘…π‘‚π‘‚=𝑅𝑅𝐢𝐢𝑣𝑣𝑖𝑖=π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”π‘Ÿπ‘Ÿπœ‹πœ‹π‘Ÿπ‘Ÿπœ‹πœ‹+𝑅𝑅𝑔𝑔𝑖𝑖𝑔𝑔
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Basic Amp Circuit Configurations: CS/CEβ€’BJT CE amplifieroIncludeRLoOverall vsig-to-vOV-gain includingRLoFinite rΟ€affects V-gain82EE100A Wang UCRπΊπΊπ‘£π‘£β‰‘οΏ½π‘£π‘£π‘‚π‘‚π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”π‘…π‘…πΏπΏβ‰ βˆž=𝑣𝑣𝑖𝑖𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=βˆ’π‘Ÿπ‘Ÿπœ‹πœ‹π‘Ÿπ‘Ÿπœ‹πœ‹+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔𝑔𝑔𝑔𝑔(𝑅𝑅𝐢𝐢βˆ₯ 𝑅𝑅𝐿𝐿)𝐴𝐴𝑣𝑣=𝐴𝐴𝑣𝑣𝑝𝑝𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂=βˆ’π‘”π‘”π‘”π‘”(𝑅𝑅𝐢𝐢βˆ₯ 𝑅𝑅𝐿𝐿)𝑣𝑣𝑖𝑖=π‘£π‘£πœ‹πœ‹
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Example 7.8Q: A CE amplifier utilizes a BJT with Ξ² =100 is biased at IC=1 mA and has a collector resistance RC=5 kΩ. Find Rin, RO, and Avo. If the amplifier is fed with a signal source having a resistance of 5 kΩ, and a load resistance RL=5kΩis connected to the output terminal, find the resulting Avand Gv. If οΏ½π‘£π‘£πœ‹πœ‹is to be limited to 5 mV, what are the corresponding �𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔and �𝑣𝑣𝑂𝑂with the load connected? 83EE100A Wang UCR
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Example 7.8 Solutionβ€’Small-signal parameters:Thus, 84EE100A Wang UCR𝑔𝑔𝑔𝑔=𝐼𝐼𝐢𝐢𝑉𝑉𝑇𝑇=1π‘šπ‘šπ΄π΄25π‘šπ‘šπ‘‰π‘‰=40π‘šπ‘šπ΄π΄/π‘‰π‘‰π‘Ÿπ‘Ÿπœ‹πœ‹=𝛽𝛽𝑔𝑔𝑔𝑔= 2.5π‘˜π‘˜Ξ©π‘…π‘…π‘–π‘–π‘›π‘›=π‘Ÿπ‘Ÿπœ‹πœ‹= 2.5π‘˜π‘˜Ξ©π΄π΄π‘£π‘£π‘π‘β‰‘π‘£π‘£π‘‚π‘‚π‘£π‘£π‘–π‘–=βˆ’π‘”π‘”π‘”π‘”π‘…π‘…πΆπΆ=βˆ’40π‘šπ‘šπ΄π΄π‘‰π‘‰Γ—5π‘˜π‘˜Ξ©=βˆ’1200𝑉𝑉/𝑉𝑉𝑅𝑅𝑂𝑂=𝑅𝑅𝐢𝐢=5π‘˜π‘˜Ξ©π΄π΄π‘£π‘£=𝐴𝐴𝑣𝑣𝑝𝑝𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂=βˆ’π‘”π‘”π‘”π‘”(𝑅𝑅𝐢𝐢βˆ₯ 𝑅𝑅𝐿𝐿) =βˆ’100𝑉𝑉/𝑉𝑉
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Example 7.8 Solutionβ€’Small-signal parameters:β€’For peak small-signal input οΏ½π‘£π‘£πœ‹πœ‹= 5mVThus, �𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔= 15mV�𝑣𝑣𝑂𝑂= Gv�𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔= 0.5V85EE100A Wang UCR𝐺𝐺𝑣𝑣=𝐴𝐴𝑣𝑣𝑅𝑅𝑖𝑖𝑖𝑖𝑅𝑅𝑖𝑖𝑖𝑖+𝑅𝑅𝑔𝑔𝑖𝑖𝑔𝑔=βˆ’100 Γ—2.5π‘˜π‘˜Ξ©2.5π‘˜π‘˜Ξ©+5π‘˜π‘˜Ξ©=βˆ’33.3𝑉𝑉/𝑉𝑉𝑣𝑣𝑖𝑖=𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔𝑅𝑅𝑖𝑖𝑖𝑖𝑅𝑅𝑖𝑖𝑖𝑖+𝑅𝑅𝑔𝑔𝑖𝑖𝑔𝑔
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’MOSFET CS + RsamplifierοƒΌAdd Source-degenerationresistance, RsοƒΌRsoffers Negative feedbackοƒΌUse T-modeloInputoV-gain 1/gmand Rsdivides viforvgs: 86EE100A Wang UCR𝑅𝑅𝑖𝑖𝑛𝑛≑𝑣𝑣𝑖𝑖𝑖𝑖𝑖𝑖=βˆžπ‘–π‘–πΊπΊ= 0𝑣𝑣𝑂𝑂=βˆ’π‘–π‘–π‘…π‘…π·π·π‘£π‘£π‘”π‘”π‘ π‘ =𝑣𝑣𝑖𝑖1π‘”π‘”π‘šπ‘š1π‘”π‘”π‘šπ‘š+𝑅𝑅𝑔𝑔=𝑣𝑣𝑖𝑖1+π‘”π‘”π‘šπ‘šπ‘…π‘…π‘”π‘”π‘–π‘–=𝑣𝑣𝑖𝑖1𝑔𝑔𝑔𝑔+𝑅𝑅𝑠𝑠= (𝑔𝑔𝑔𝑔1 +𝑔𝑔𝑔𝑔𝑅𝑅𝑠𝑠)𝑣𝑣𝑖𝑖
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’MOSFET CS + Rsamplifierβ‡’V-gainβ‡’Source degeneration: Rsreduces V-gainV-gain is the Ratioof Total-R in Drain (𝑅𝑅𝐷𝐷) to Total-R in Source (1π‘”π‘”π‘šπ‘š+𝑅𝑅𝑠𝑠)gmβ‡’effective transconductance (π‘”π‘”π‘šπ‘š1+π‘”π‘”π‘šπ‘šπ‘…π‘…π‘”π‘”)87EE100A Wang UCR𝐴𝐴𝑣𝑣𝑝𝑝≑𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=βˆ’π‘”π‘”π‘”π‘”π‘…π‘…π·π·1 +𝑔𝑔𝑔𝑔𝑅𝑅𝑠𝑠=βˆ’π‘…π‘…π·π·1𝑔𝑔𝑔𝑔+𝑅𝑅𝑠𝑠𝐺𝐺𝐺𝐺𝐺𝐺𝑒𝑒 βˆ’ 𝐺𝐺𝑑𝑑 βˆ’ π·π·π‘Ÿπ‘ŸπΊπΊπ‘–π‘–π·π· 𝑉𝑉𝑑𝑑𝑉𝑉𝐺𝐺𝐺𝐺𝑔𝑔𝑒𝑒 𝐺𝐺𝐺𝐺𝑖𝑖𝐷𝐷=βˆ’π‘‡π‘‡π‘‘π‘‘πΊπΊπΊπΊπ‘‰π‘‰ βˆ’ 𝑅𝑅 𝑖𝑖𝐷𝐷 π·π·π‘Ÿπ‘ŸπΊπΊπ‘–π‘–π·π·π‘‡π‘‡π‘‘π‘‘πΊπΊπΊπΊπ‘‰π‘‰ βˆ’ 𝑅𝑅 𝑖𝑖𝐷𝐷 π‘†π‘†π‘‘π‘‘π‘†π‘†π‘Ÿπ‘Ÿπ‘†π‘†π‘’π‘’
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’MOSFET CS + RsamplifieroOutput oV-gain includingRLoOverall vsig-to-vOV-gain includingRLThus 88EE100A Wang UCR𝑅𝑅𝑂𝑂=𝑅𝑅𝐷𝐷𝐴𝐴𝑣𝑣≑𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=βˆ’π‘”π‘”π‘”π‘”(𝑅𝑅𝐷𝐷βˆ₯ 𝑅𝑅𝐿𝐿)1 +𝑔𝑔𝑔𝑔𝑅𝑅𝑠𝑠=βˆ’π‘…π‘…π·π·βˆ₯ 𝑅𝑅𝐿𝐿1𝑔𝑔𝑔𝑔+𝑅𝑅𝑠𝑠𝑅𝑅𝑖𝑖𝑛𝑛=βˆžπ‘£π‘£π‘–π‘–=π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”πΊπΊπ‘£π‘£β‰‘οΏ½π‘£π‘£π‘‚π‘‚π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”π‘…π‘…πΏπΏβ‰ βˆž=𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=𝐴𝐴𝑣𝑣
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’BJT CE + ReamplifierοƒΌAdd Emitter-degenerationresistance, ReοƒΌReoffers Negative feedbackοƒΌSolution oInputThus 89EE100A Wang UCR𝑅𝑅𝑖𝑖𝑛𝑛≑𝑣𝑣𝑖𝑖𝑖𝑖𝑏𝑏≠ π‘Ÿπ‘Ÿπœ‹πœ‹π‘–π‘–π‘π‘= (1βˆ’ 𝛼𝛼)𝑖𝑖𝑐𝑐=𝑖𝑖𝑏𝑏𝛽𝛽+1𝑖𝑖𝑐𝑐=π‘£π‘£π‘–π‘–π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑏𝑏𝑅𝑅𝑖𝑖𝑛𝑛= (1 +𝛽𝛽)(π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐)
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’BJT CE + ReamplifierοƒΌRe impact on RinoResistance-reflectionrule:Rinlooking into Base is (1+Ξ²) times of total-R in EmitteroRe increases Rin,90EE100A Wang UCR𝑅𝑅𝑖𝑖𝑛𝑛= (1 +𝛽𝛽)(π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐)𝑅𝑅𝑖𝑖𝑛𝑛(𝑀𝑀𝑖𝑖𝐺𝐺𝑀 𝑅𝑅𝑐𝑐)𝑅𝑅𝑖𝑖𝑛𝑛(𝐷𝐷𝑑𝑑 𝑅𝑅𝑐𝑐)=(1 +𝛽𝛽)(π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐)(1 +𝛽𝛽)π‘Ÿπ‘Ÿπ‘π‘= 1 +π‘…π‘…π‘π‘π‘Ÿπ‘Ÿπ‘π‘β‰ƒ1 +𝑔𝑔𝑔𝑔𝑅𝑅𝑐𝑐
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’BJT CE + ReamplifieroV-gain Thus oAlternatively, β‡’Re reduces gain91EE100A Wang UCR𝐴𝐴𝑣𝑣𝑝𝑝≑𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=βˆ’π›Όπ›Όπ‘…π‘…πΆπΆπ‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐𝑣𝑣𝑂𝑂=βˆ’π‘–π‘–π‘π‘π‘…π‘…πΆπΆ=βˆ’π›Όπ›Όπ‘–π‘–π‘π‘π‘…π‘…πΆπΆπ΅π΅πΊπΊπ΅π΅π‘’π‘’ βˆ’ 𝐺𝐺𝑑𝑑 βˆ’ πΆπΆπ‘‘π‘‘π‘‰π‘‰π‘‰π‘‰π‘’π‘’π‘†π‘†πΊπΊπ‘‘π‘‘π‘Ÿπ‘Ÿ 𝑉𝑉𝑑𝑑𝑉𝑉𝐺𝐺𝐺𝐺𝑔𝑔𝑒𝑒 𝐺𝐺𝐺𝐺𝑖𝑖𝐷𝐷=βˆ’π›Όπ›Όπ‘‡π‘‡π‘‘π‘‘πΊπΊπΊπΊπ‘‰π‘‰ βˆ’ 𝑅𝑅 𝑖𝑖𝐷𝐷 πΆπΆπ‘‘π‘‘π‘‰π‘‰π‘‰π‘‰π‘’π‘’π‘†π‘†πΊπΊπ‘‘π‘‘π‘Ÿπ‘Ÿπ‘‡π‘‡π‘‘π‘‘πΊπΊπΊπΊπ‘‰π‘‰ βˆ’ 𝑅𝑅 𝑖𝑖𝐷𝐷 πΈπΈπ‘šπ‘šπ‘–π‘–πΊπΊπΊπΊπ‘’π‘’π‘Ÿπ‘Ÿπ΄π΄π‘£π‘£π‘π‘=βˆ’π›Όπ›Όπ‘…π‘…πΆπΆπ‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐=βˆ’π›Όπ›Όπ‘Ÿπ‘Ÿπ‘π‘π‘…π‘…πΆπΆ1 +π‘…π‘…π‘π‘π‘Ÿπ‘Ÿπ‘π‘=βˆ’π‘”π‘”π‘”π‘”π‘…π‘…πΆπΆ1 +π‘…π‘…π‘π‘π‘Ÿπ‘Ÿπ‘π‘β‰ƒ βˆ’π‘”π‘”π‘”π‘”π‘…π‘…πΆπΆ1 +𝑔𝑔𝑔𝑔𝑅𝑅𝑐𝑐
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’BJT CE + ReamplifieroOutput oIncludeRLoOverall vsig-to-vOV-gain includingRL92EE100A Wang UCRπΊπΊπ‘£π‘£β‰‘οΏ½π‘£π‘£π‘‚π‘‚π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”π‘…π‘…πΏπΏβ‰ βˆž=𝑣𝑣𝑖𝑖𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=𝑅𝑅𝑖𝑖𝑛𝑛𝑅𝑅𝑖𝑖𝑛𝑛+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔𝐴𝐴𝑣𝑣=βˆ’π›½π›½(𝑅𝑅𝐢𝐢βˆ₯ 𝑅𝑅𝐿𝐿)𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔+ (𝛽𝛽+ 1)(π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐)𝐴𝐴𝑣𝑣=𝐴𝐴𝑣𝑣𝑝𝑝𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂=βˆ’π›Όπ›Όπ‘…π‘…πΆπΆπ‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑏𝑏𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝐢𝐢=βˆ’π›Όπ›Ό(𝑅𝑅𝐢𝐢βˆ₯𝑅𝑅𝐿𝐿)π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑏𝑏𝑅𝑅𝑂𝑂=𝑅𝑅𝐢𝐢
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Basic Amp Circuit Configurations: CS/CE + Rs/Reβ€’BJT CE + ReamplifieroReImpact on Gv?Gvreduces due to Re(Emitter degeneration) oKeep vΟ€= voltage across B-E93EE100A Wang UCR𝐺𝐺𝑣𝑣(𝑅𝑅𝑐𝑐𝑖𝑖𝐷𝐷𝑆𝑆𝑉𝑉𝑆𝑆𝑑𝑑𝑒𝑒𝑑𝑑) =βˆ’π›½π›½(𝑅𝑅𝐢𝐢βˆ₯ 𝑅𝑅𝐿𝐿)𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔+ (𝛽𝛽+ 1)(π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐)𝐺𝐺𝑣𝑣(𝐷𝐷𝑑𝑑 𝑅𝑅𝑐𝑐) =βˆ’π›½π›½(𝑅𝑅𝐢𝐢βˆ₯ 𝑅𝑅𝐿𝐿)𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔+ (𝛽𝛽+ 1)π‘Ÿπ‘Ÿπ‘π‘π‘£π‘£πœ‹πœ‹π‘£π‘£π‘–π‘–=π‘Ÿπ‘Ÿπ‘π‘π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐≅11 +𝑔𝑔𝑔𝑔𝑅𝑅𝑐𝑐
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Example 7.9Q: For the CE amplifier specified in Example 7.8, what value of Reis needed to raise Rinto a value fourtimes that of Rsig? With Reincluded, find Avo, RO, Av, and Gv. Also, if οΏ½π‘£π‘£πœ‹πœ‹is to be limited to 5 mV, what are the corresponding �𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔and �𝑣𝑣𝑂𝑂? 94EE100A Wang UCR
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Example 7.9 Solutionβ€’From Example 7.8 (add Re)β€’For 4x: β€’Use Thus, β€’Reincluded:95EE100A Wang UCR𝑔𝑔𝑔𝑔=40π‘šπ‘šπ΄π΄/𝑉𝑉𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔=5π‘˜π‘˜Ξ©π‘…π‘…π‘π‘β‰…175Ω𝑅𝑅𝑖𝑖𝑛𝑛= 4 ×𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔= 4 Γ—5π‘˜π‘˜Ξ©= 20π‘˜π‘˜Ξ©π‘…π‘…π‘–π‘–π‘›π‘›= (1 +𝛽𝛽)(π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐)π‘Ÿπ‘Ÿπœ‹πœ‹= (1 +𝛽𝛽)π‘Ÿπ‘Ÿπ‘π‘π‘Ÿπ‘Ÿπœ‹πœ‹= 2.5π‘˜π‘˜Ξ©π΄π΄π‘£π‘£π‘π‘=βˆ’π›Όπ›Όπ‘…π‘…πΆπΆπ‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑏𝑏=βˆ’25𝑉𝑉/𝑉𝑉
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Example 7.9 Solutionβ€’Output-R unchanged: β€’For peak small-signal input οΏ½π‘£π‘£πœ‹πœ‹= 5mVUse Thus 96EE100A Wang UCR𝐺𝐺𝑣𝑣=𝐴𝐴𝑣𝑣𝑅𝑅𝑖𝑖𝑖𝑖𝑅𝑅𝑖𝑖𝑖𝑖+𝑅𝑅𝑔𝑔𝑖𝑖𝑔𝑔=βˆ’12.5 Γ—20π‘˜π‘˜Ξ©20π‘˜π‘˜Ξ©+5π‘˜π‘˜Ξ©=βˆ’10𝑉𝑉/𝑉𝑉𝑣𝑣𝑖𝑖=𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔𝑅𝑅𝑖𝑖𝑖𝑖𝑅𝑅𝑖𝑖𝑖𝑖+𝑅𝑅𝑔𝑔𝑖𝑖𝑔𝑔𝐴𝐴𝑣𝑣=𝐴𝐴𝑣𝑣𝑝𝑝𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂=βˆ’25 Γ—55+5=βˆ’12.5𝑉𝑉/𝑉𝑉𝑅𝑅𝑂𝑂=𝑅𝑅𝐢𝐢=5π‘˜π‘˜Ξ©π‘£π‘£πœ‹πœ‹π‘£π‘£π‘–π‘–=π‘Ÿπ‘Ÿπ‘π‘π‘Ÿπ‘Ÿπ‘π‘+𝑅𝑅𝑐𝑐�𝑣𝑣𝑖𝑖=οΏ½π‘£π‘£πœ‹πœ‹π‘Ÿπ‘Ÿπ‘π‘+π‘…π‘…π‘π‘π‘Ÿπ‘Ÿπ‘π‘=40π‘šπ‘šπ‘‰π‘‰οΏ½π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”=�𝑣𝑣𝑖𝑖𝑅𝑅𝑖𝑖𝑛𝑛+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔𝑅𝑅𝑖𝑖𝑛𝑛=50π‘šπ‘šπ‘‰π‘‰οΏ½π‘£π‘£π‘‚π‘‚=�𝑣𝑣𝑠𝑠𝑖𝑖𝑔𝑔𝐺𝐺𝑣𝑣= 50 Γ— 10 = 0.5𝑉𝑉
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Basic Amp Circuit Configurations: CG/CBβ€’MOSFET CG amplifierοƒΌSignal source: vsig, RsigοƒΌRDis part of amplifier, RD||RLοƒΌUse T-modelοƒΌSolution oInput-R is lowoV-gain Thus Non-invertinggainοƒ˜Compare with CS: οƒΌLow-Rinseverely attenuates vsigβ‡’reduce overall-gain97EE100A Wang UCR𝑅𝑅𝑖𝑖𝑛𝑛≑𝑣𝑣𝑖𝑖𝑖𝑖𝑖𝑖=1𝑔𝑔𝑔𝑔𝐴𝐴𝑣𝑣𝑝𝑝≑𝑣𝑣𝑂𝑂𝑣𝑣𝑖𝑖=𝑔𝑔𝑔𝑔𝑅𝑅𝐷𝐷𝑖𝑖=βˆ’π‘£π‘£π‘–π‘–1𝑔𝑔𝑔𝑔𝑣𝑣𝑂𝑂=βˆ’π‘–π‘–π‘…π‘…π·π·π‘£π‘£π‘–π‘–π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”=𝑅𝑅𝑖𝑖𝑛𝑛𝑅𝑅𝑖𝑖𝑛𝑛+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔=1𝑔𝑔𝑔𝑔1𝑔𝑔𝑔𝑔+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔
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Basic Amp Circuit Configurations: CG/CBβ€’MOSFET CG amplifieroOutput oIncludeRLoOverall vsig-to-vOV-gain includingRLοƒΌReduction (~CS)98EE100A Wang UCRπΊπΊπ‘£π‘£β‰‘οΏ½π‘£π‘£π‘‚π‘‚π‘£π‘£π‘ π‘ π‘–π‘–π‘”π‘”π‘…π‘…πΏπΏβ‰ βˆž=1𝑔𝑔𝑔𝑔1𝑔𝑔𝑔𝑔+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔𝑔𝑔𝑔𝑔(𝑅𝑅𝐷𝐷βˆ₯ 𝑅𝑅𝐿𝐿) =(𝑅𝑅𝐷𝐷βˆ₯ 𝑅𝑅𝐿𝐿)1𝑔𝑔𝑔𝑔+𝑅𝑅𝑠𝑠𝑖𝑖𝑔𝑔𝐴𝐴𝑣𝑣=𝐴𝐴𝑣𝑣𝑝𝑝𝑅𝑅𝐿𝐿𝑅𝑅𝐿𝐿+𝑅𝑅𝑂𝑂=𝑔𝑔𝑔𝑔(𝑅𝑅𝐷𝐷βˆ₯ 𝑅𝑅𝐿𝐿)𝑅𝑅𝑂𝑂=𝑅𝑅𝐷𝐷Overall𝑉𝑉𝑑𝑑𝑉𝑉𝐺𝐺𝐺𝐺𝑔𝑔𝑒𝑒 𝐺𝐺𝐺𝐺𝑖𝑖𝐷𝐷=π‘‡π‘‡π‘π‘π‘‘π‘‘π‘”π‘”π‘‡π‘‡βˆ’π‘…π‘… 𝑖𝑖𝑛𝑛 π·π·π‘Ÿπ‘Ÿπ‘”π‘”π‘–π‘–π‘›π‘›π‘‡π‘‡π‘π‘π‘‘π‘‘π‘”π‘”π‘‡π‘‡βˆ’π‘…π‘… 𝑖𝑖𝑛𝑛 πΊπΊπ‘π‘π‘†π‘†π‘Ÿπ‘Ÿπ‘π‘π‘π‘
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