1CESS3005CSE112MajorTaskstudents (1) (1)
.pdf
School
Ain Shams University**We aren't endorsed by this school
Course
COMPUTER E CSE332
Subject
Electrical Engineering
Date
Dec 30, 2024
Pages
6
Uploaded by MajorSpider186
Ain Shams University Faculty of Engineering Computer Engineering and Software Systems Course Assessment Map and Specification CESS3005: Computer Architecture Major Task: MIPS Design using VHDL Introduction This coursework is to be carried out in groups of 5 students. It is designed to meet the module Learning Outcomes as presented in the module proforma. Project description: 1.A design of MIPS processor using VHDL that illustrates a basic computer system by simulating the data and control paths. 2.The project is done in two phases.3.You should present the projectto the TA, and be prepared for a 10 minutes discussion. 4.You should submit a fully detailed and described project reportin soft copy. 5.This coursework is to be carried out in groups of 5 students.Phase I Instructions: 1. Please reference appropriately any documents or URLs or books you use. 2. Assessment weight is 50%. 3. The due date of this Assignment is 10 August 2024. 4. Only electronic submissions, through the e-learning web site, will be accepted. 5. Submissions are only accepted in form of one zip file containing the vhd files. 6. You are encouraged to ask the module leader and TA for any clarifications. 7. Late submissions will not be accepted. Requirements: 1- Implement the MIPS register file that reads simultaneously from two registers and write into another. •The main module should be called "RegisterFile".. •The entity should look as follows: oread_sel1 : in std_logic_vector(4 downto 0) oread_sel2 : in std_logic_vector(4 downto 0) owrite_sel : in std_logic_vector(4 downto 0) owrite_ena : in std_logic oclk: in std_logic owrite_data: in std_logic_vector(31 downto 0) odata1: out std_logic_vector(31 downto 0) odata2: out std_logic_vector(31 downto 0)
2- Modify the 32 bit full ALU. •ALU functional specifications: ALUOpFunction0000AND 0001OR 0010ADD 0110SUB 1100 NOR 0111 STL •Entity should look as follows: odata1 : in std_logic_vector(31 downto 0) odata2 : in std_logic_vector(31 downto 0) oaluop : in std_logic_vector(3 downto 0) odataout: out std_logic_vector(31 downto 0) zflag: out std_logic 3- Connect the already-built modules including register file, ALU, to design a simple MIPS CPU Using VHDL. The proposed CPU should be able to perform certain instructions: R-type (AND, OR, ADD, SUB, SLT and NOR). •The datapath entity should look as follows: oport(clk, reset: in STD_LOGIC; oinstr: in STD_LOGIC_VECTOR(31 downto0);oaluoperation: in STD_LOGIC_VECTOR(3 downto0); ozero: out STD_LOGIC; oregwrite: in STD_LOGICoaluout : buffer STD_LOGIC_VECTOR(31 downto0)); oMarking: The VHDL code and a report with the following: •VHDL coding of blocks [40%] •Simulation of blocks [40%] •Pass all test cases [20%] Phase II Instructions: 1. Please reference appropriately any documents or URLs or books you use. 2. Assessment weight is 60%. 3. The due date of this Assignment is 20 May 2023. 4. Only electronic submissions, through the e-learning web site, will be accepted. 5. Submissions are only accepted in form of one zip file containing the vhd files. 6. You are encouraged to ask the module leader and TA for any clarifications. 7. Late submissions will not be accepted. Requirements: Modify the MIPS CPU as to be able to perform not only R instructions, but also I-type (lw, sw, beq) and J instruction.
Steps: •Implement the controlmodule, which is responsible for all of the control signals. •Implement the Mips module by connecting the datapath with the control module . •Connect the Mipsmodule with instruction and data memory module together. •Fill the memory module by a simple program. •The CPU should be able to execute this program. •Simulate the results and check the final results The following diagram shows the abstract CPU design Main_module Entity should look as follows:•CLK: IN STD_LOGIC;•RST: IN STD_LOGIC;•Writedata,dataadr:OUT STD_LOGIC_VECTOR(31 downto 0);•memwrite: OUT STD_LOGIC;
Test Case: Marking: The VHDL code and a report with the following: •VHDL coding of blocks [40%] •Simulation of blocks [40%] •Pass all test cases [20%] What you should hand in Student should submit his/her work as a digital presentation which he/she will present in front of the TA and other students. In addition, student should submit the project output as a VHDL code and a report.The Report should also include the following: - A brief description of your implementation and design choices.
- The Data path you used including any necessary extensions you added to support all the required instructions. - Sample output - Any Assumptions you added that are not standard - A section showing the contribution of each student in the project (Who did what exactly and the percentage of the overall effort every one made)Evaluation Criteria The following criteria nay be updated according to the instructor evaluation criteria and the needed level of achievement. 89% and above: Your work must be of outstanding quality and fully meet the requirements of the coursework specification and learning outcomes stated. You must show independent thinking and apply this to your work showing originality and consideration of key issues. There must be evidence of wider reading on the subject. In addition, 76% - 89%: Your work must be of good quality and meet the requirements of the coursework specification and learning outcomes stated. You must demonstrate some originality in your work and show this by applying new learning to the key issues of the coursework. There must be evidence of wider reading on the subject. In addition 67% - 76%: Your work must be comprehensive and meet all of the requirements stated by the coursework specification and learning outcomes. You must show a good understanding of the key concepts and be able to apply them to solve the problem set by the coursework. There must be enough depth to your work to provide evidence of wider reading. 60% - 67%: Your work must be of a standard that meets the requirements stated by the coursework specification and learning outcomes. You must show a reasonable level of understanding of the key concepts and principles and you must have applied this knowledge to the coursework problem. There should be some evidence of wider reading. In addition Below 60%: Your work is of poor quality and does not meet the requirements stated by the coursework specification and learning outcomes. There is a lack of understanding of key concepts and knowledge and no evidence of wider reading. Academic Misconduct The University defines Academic Misconduct as ‘any case of deliberate, premeditated cheating, collusion, plagiarism or falsification of information, in an attempt to deceive and gain an unfair advantage in assessment’. This includes attempting to gain marks as part of a team without making a contribution. The department takes Academic Misconduct very seriously and any suspected cases will be investigated through the University’s standard policy. If you are found guilty, you may be expelled from the University with no award. It is your responsibility to ensure that you understand what constitutes Academic Misconduct and to ensure that you do not break the rules. If you are unclear about what is required, please ask.
Exam ILOs according to UEL module specs Knowledge 1. Explain the concept of combinational and sequential logic circuits. (COI) 2. Illustrate how a data-path with or without pipelining is designed. (COI) 3. Infer the effect of the memory hierarchy on performance. (COI) Thinking skills 4. Simplify logic circuits using Boolean algebra and Karnaugh maps. (COI) 5. Analyse and design combinational and sequential logic circuits. (COI) 6. Write MIPS assembly programs and translate C programs to assembly as well as assembly programs to machine code. (COI, DP, IC) Subject-based practical skills 7. Design the digital computer components and processor’s data path. (COI, DP, IC)Skills for life and work (general skills) 8. Work and communicate effectively in team by effective collaboration and task management, working in a constrained stressful environment, and leading and motivating individuals. (SEI, PI, IC)Course Assessment 2 3 6 7 8 Points Phase I••••10 II ••••10 20