Sheet No.3 - Sol
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School
University Of Chicago**We aren't endorsed by this school
Course
ECE 480
Subject
Electrical Engineering
Date
Jan 7, 2025
Pages
2
Uploaded by AmbassadorThunder2396
1 1.Consider four designs of a 6-input AND gate shown in Figure. Develop an expression for the delay of each path if the path electrical effort is H. What design is fastest for H = 1? For H = 5? For H = 20? Explain your conclusions intuitively. D = N(GH)1/N+ P. Compare in a spreadsheet. Design (b) is fastest for H = 1 or 5. Design (d) is fastest for H = 20 because it has a lower logical effort and more stages to drive the large path effort. (c) is always worse than (b) because it has greater logical effort, all else being equal. 2.Consider a process in which pMOS transistors have three times the effective resistance as nMOS transistors. A unit inverter with equal rising and falling delays in this process is shown in Figure. Calculate the logical efforts of a 2-input NAND gate and a 2-input NOR gate if they are designed with equal rising and falling delays. NAND2: g = 5/4; NOR2: g = 7/4. The inverter has a 3:1 P/N ratio and 4 units of capacitance. The NAND has a 3:2 ratio and 5 units of capacitance, while the NOR has a 6:1 ratio and 7 units of capacitance. 3.Generalize Exercise 2 if the pMOS transistors have μtimes the effective resistance of nMOS transistors. Find a general expression for the logical efforts First semester 2022/2023 Dr. Rania Fouad TA/ Muhammad Dakheel Fayoum UniversityFaculty of EngineeringDepartment of ElectricalEngineering Electronics 6 - ECE 401 Sheet No.3 –Solutions
2 of a k input NAND gate and a k-input NOR gate. As μincreases, comment on the relative desirability of NANDs vs. NORs. NAND: g = (μ + k) / (μ + 1); NOR: g = (μk + 1) / (μ + 1). As μ increases, NOR gates get worse compared to NAND gates because the series pMOS devices become more expensive. 4.The clock buffer in Figure can present a maximum input capacitance of 100 fF. Both true and complementary outputs must drive loads of 300 fF. Compute the input capacitance of each inverter to minimize the worst-case delay from input to either output. What is this delay, in Y ? Assume the inverter parasitic delay is 1. If the first upper inverter has size x and the lower 100-x and the second upper inverter has the same stage effort as the first (to achieve least delay), the least delays are: D = 2(300/x)1/2+ 2 = 300/(100-x) + 1. Hence x = 49.4, D = 6.9 τ, and the sizes are 49.4 and 121.7 for the upper inverters and 50.6 for the lower inverter.