Nt1310 Unit 3 Flow Analysis

This block performs the flow table (hash table) lookup, updates the per port packet and byte counters and reads the corresponding actions. If the packet header does not match the corresponding hash table entries, then it is considered as a table miss and the packet is dropped. First, the structure of hash table and hashing function are described and then the functionality of exact match is described.
The hash table is constructed using 512 deep and 64 bit wide block RAM (BRAM). The hash table can support 32 different flows with each flow occupying 16 entries in the hash table. Cyclic redundancy code (CRC) is used as the hashing function. The pseudo code to form the hash indices is shown below
//Pad the 248 bit header to form 256 bit data
Data = {8’d0,flow_hdr}
//Reverse the bits in data
Data_Rev = bit_reverse(Data)
//Consider last 5 bits to identify a flow between 0 and 31
//Polynomial for Hash0 = 0x04C11DB7
Hash0 = CRC32_FUNC_0(Data_Rev)%5;
//Polynomial for Hash1 = 0x1EDC6F41
Hash1 = CRC32_FUNC_1(Data_Rev)%5;
The exact match block reads the flow header present in the address hash0 × 16 and hash1 × 16 (multiplied with 16, as each flow is 16 deep). This flow

The current design has a Microblaze processor accompanied by multiple programmable hardware packet drivers. Each of these drivers contain a small buffer to hold one packet and it transmits this packet to the switch interface at the programmed rate. The processor writes a packet in to the buffer, sets the rate and sets the control to start the driver. Similarly, the processor can set the control to stop the driver as well. Figure 3.6 shows the complete design. The Microblaze processor communicates with the FSL interface block using FSL. The processor sends the data and control information in 3 instructions. This is packed in to one line by the FSL interface block and forwarded to the corresponding packet driver. All the packet drivers are connected to the FSL interface block in a daisy chain fashion. There is